Modern computers and other digital systems rely on semiconductor memory devices to store data and instructions for processing by a central processing unit (CPU). Most of these systems have a system memory, which usually includes Dynamic Random Access Memory (DRAM) devices. The memory storage cost per bit for DRAM devices is relatively low because a DRAM memory cell needs relatively few circuit components to store a data bit as compared with other types of memory cells, such as Static Random Access Memory (SRAM) devices or Flash memory devices. Thus, a high capacity system memory can be implemented using DRAM devices for a relatively low cost.
Although DRAM devices have the advantage of providing relatively low-cost data storage, they generally consume more power. In fact, DRAM devices used in a digital system, such as a computer, can consume a significant percentage of the total power consumed by the system. The power consumed by computers and other digital systems can be a critical factor in their utility in certain applications. For example, the power consumed by portable personal computers greatly affects the length of time they can be used without the need to recharge batteries powering such computers. Power consumption can also be important even where memory devices are not powered by batteries because it may be necessary to limit the heat generated by the memory devices.
Furthermore, as is well known in the art, DRAM memory cells must be periodically refreshed to retain data stored in the DRAM device by restoring the charge on each bit. This refresh operation tends to consume power at a substantial rate. Refresh is typically performed by activating each row of memory cells in an array, which essentially reads data bits from the memory cells in each row and then internally writes those same data bits back to the same cells in the row. This refresh is generally performed at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes. Since refresh involves accessing data bits in a large number of memory cells at a rapid rate, refresh tends to be a particularly power-hungry operation. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
The amount of power consumed by refresh also depends on which of several refresh modes is active. A self-refresh mode is normally active during periods when data are not being read from or written to the DRAM device. Since many electronic devices, such as notebook computers, are often inactive for substantial periods of time, the amount of power consumed during self-refresh can be an important factor in determining how long the electronic device can be used after a battery charge. While power is also consumed at a significant rate during other refresh modes when the DRAM device is active, the DRAM device is consuming power at a significant rate anyway while the data stored therein are being accessed. Therefore, if the power consumption during self-refresh can be reduced, the rate of power consumption dedicated to refresh operations can be significantly reduced.
Furthermore, DRAM devices have been proposed with prolonged low power modes (often referred to as “sleep modes”) for maintaining the data in the DRAM when the DRAM is not being externally accessed for a relatively long period of time. During the sleep modes, the DRAM may return to an intermediate power level to perform the required periodic refresh cycles.
Another method for reducing power consumption in DRAMs is to modify the refresh period as a function of temperature. The rate at which charge leaks from a DRAM memory cell increases with temperature. The refresh rate must be sufficiently high to ensure that no data is lost at the highest temperature in the specified range of operating temperatures of the DRAM device. Yet, DRAM devices normally operate at temperatures that are substantially lower than their maximum operating temperature. Therefore, DRAM devices are generally refreshed at a rate that is higher than the rate actually needed to prevent data from being lost, and, in doing so, unnecessarily consume power. To address this problem, some commercially available DRAM devices allow the user to program a mode register to select a lower maximum operating temperature. The DRAM device then adjusts the refresh rate to correspond to the maximum operating temperature selected by the user. Although adjusting the refresh rate to correspond to a lower maximum operating temperature does reduce the rate of power consumed during refresh, it nevertheless still allows power to be consumed at a significant rate. If the refresh rate was reduced beyond a safe limit, at least some of the memory cells might not be refreshed before that data stored therein was lost. Data subsequently read from the DRAM device would then contain erroneous data bits.